A conventional computer system supporting multi-display to show images on different display devices at the same time is schematically shown in FIG. 1. The computer system comprises a frame buffer 10, a first display engine 11, a second display engine 12, a first-in-first-out (FIFO) buffer 14, a first multiplexer 15, a second multiplexer 16, a phase-lock loop (PLL) clock generator 19 and a spread spectrum clock (SSC) generator 20. The frame buffer 10 stores therein image data. By processing image data in parallel with the first display engine 11 and the second display engine 12, different images can be displayed on a cathode ray tube (CRT) monitor 21 and a liquid crystal display (LCD) monitor 22, respectively. Alternatively, with the arrangement of the first multiplexer 15 and the second multiplexer 16, either of the first display engine 11 and the second display engine 12 can be used to simultaneously display the same image on the CRT monitor 21 and the LCD display 22 so as to perform a multi-display function.
The phase-lock loop (PLL) clock generator 19 is used to generate a clock signal referred to control transmission of image data. Since a PLL clock generator conventionally designed for a CRT monitor has a narrow frequency spectrum, it is not suitable to be directly applied to an LCD display that a severe electromagnetic interference (EMI) stipulation is concerned. Otherwise, the LCD display is likely to fail to pass the EMI test. Therefore, the first-in-first-out (FIFO) buffer 14 and spread spectrum clock (SSC) generator 20 are arranged between the PLL clock generator 19 and the LCD 22 for reducing the EMI emission of the LCD display 22. In response to a clock signal LCDCLK generated by the PLL clock generator 19, the data writing index of the FIFO buffer 14 moves. On the other hand, the SSC generator 20 spreads the frequency spectrum of the clock signal LCDCLK to generate a spread spectrum clock signal SSCLK. In response to the spread spectrum clock signal SSCLK, the data reading index of the FIFO buffer 14 moves. In this way, the clock signal LCDCLK having a narrow frequency spectrum can be dispersed.
Since the frequency of the spread spectrum clock signal SSCLK generally varies with time, the frequency difference between the spread spectrum clock signal SSCLK and the clock signal LCDCLK may lead to operational errors in reading/writing the FIFO buffer 14. For example, so-called “overflow” that the address of the data writing index leading the address of the data reading index may happen. This overflow phenomenon will result in abnormal display.